Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance–voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling

First Demonstration of High Temperature SiC CMOS Gate Driver in Bridge Leg for Hybrid Power Module Application

A high-temperature silicon carbide power module using CMOS gate drive technology and discrete power devices is presented. The power module was aged at 200V and 300 °C for 3,000 hours in a long-term reliability test. After the initial increase, the variation in the rise time of the module is 27% (49.63ns@1,000h compared to 63.1ns@3,000h), whilst the fall time increases by 54.3% (62.92ns@1,000h compared to 97.1ns@3,000h). The unique assembly enables the integrated circuits of CMOS logic with passive circuit elements capable of operation at temperatures of 300°C and beyond

Instability of phosphorous doped SiO2 in 4H-SiC MOS capacitors at high temperatures

In this paper, the effect of inclusion of phosphorous (at a concentration below 1%) on the high temperature characteristics (up to 300 °C) of the SiO2/SiC interface is investigated. Capacitance–voltage measurements taken for a range of frequencies have been utilized to extract parameters including flatband voltage, threshold voltage, effective oxide charge, and interface state density. The variation of these parameters with temperature has been investigated for bias sweeps in opposing directions and a comparison made between phosphorous doped and as-grown oxides. At room temperature, the effective oxide charge for SiO2 may be reduced by the phosphorous termination of dangling bonds at the interface. However, at high temperatures, the effective charge in the phosphorous doped oxide remains unstable and effects such as flatband voltage shift and threshold voltage shift dominate the characteristics. The instability in these characteristics was found to result from the trapped charges in the oxide (±1012 cm−3) or near interface traps at the interface of the gate oxide and the semiconductor (1012–1013 cm−2 eV−1). Hence, the performance enhancements observed for phosphorous doped oxides are not realised in devices operated at elevated temperatures